This application contains subject matter similar to subject matter disclosed in copending U.S. patent application Ser. No. 09/713,313 filed on Nov. 16, 2000, copending U.S. patent application Ser. No. 09/593,231 filed on Jun. 14, 2000, and copending U.S. patent application Ser. No. 09/655,699 filed on Sep. 6, 2000.
The present invention relates to a semiconductor device comprising a high conductivity interconnect structure, and to a method of forming the high conductivity interconnect structure. The present invention is applicable to high speed integrated circuits, particularly integrated circuits having sub-micron design features.
As integrated circuit geometry continues to plunge into the deep sub-micron regime, it becomes increasingly difficult to satisfy the requirements of high performance microprocessor applications for rapid circuitry speed. The speed of semiconductor circuitry varies inversely with the resistance (R) and capacitance (C) of the interconnection system. The higher the value of the Rxc3x97C product, the more limiting the circuit operating speed. Miniaturization requires long interconnects having small contacts and small cross-sections. Accordingly, continuing reduction of design rules into the deep sub-micron regime requires decreasing the R and C associated with interconnection paths. Thus, low resistivity interconnection paths are critical to fabricating dense, high performance devices.
One way to increase the control speed of semiconductor circuitry is to reduce the resistance of a conductive pattern. Copper (Cu) is considered a viable alternative to aluminum (Al) for metallization patterns, particularly for interconnect systems having smaller dimensions. Cu has a lower bulk resistivity and potentially higher electromigration tolerance than Al. Both the lower bulk resistivity and higher electromigration tolerance improve circuit performance. A conventional approach to forming a Cu interconnection involves the use of damascene processing in which openings are formed in an interlayer dielectric (ILD) and then filled with Cu. Such damascene techniques typically include single as well as dual damascene techniques, the latter comprising forming a via opening in communication with a trench opening and simultaneously filling by metal deposition to form a via in communication with a metal line.
However, Cu is a mid-gap impurity in silicon and silicon dioxide. Accordingly, Cu diffusion through interlayer dielectrics, such as silicon dioxide, degrades the performance of the integrated circuit. A conventional approach to the diffusion problem comprises depositing a barrier material to encapsulate the Cu line. Typically diffusion barrier materials include tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), titanium tungsten (TiW), and silicon nitride for encapsulating Cu. The use of such barrier materials to encapsulate Cu is not limited to the interface between the Cu and the ILD, but includes interfaces with other metals as well. In depositing Cu by electroless deposition or electroplating, a seedlayer is also typically deposited to catalyze electroless deposition or to carry electric current for electroplating. For electroplating, the seedlayer must be continuous. However, for electroless plating, very thin catalytic layers can be employed in the form of islands.
Conventional Cu interconnect methodology typically comprises planarizing after Cu deposition, as by chemical-mechanical polishing (CMP), such that the upper surfaces of the filled trenches are substantially coplanar with the upper surface of the ILD. Subsequently a capping layer, such as silicon nitride, is deposited to complete encapsulation of the Cu inlaid metallization. However, adhesion of such a capping layer as to the Cu inlaid metallization has been problematic, and Cu diffusion along the surface of the interface with the capping layer has been found to be a major cause of electromigration failure.
Conventional semiconductor manufacturing processes typically comprise forming a metal level having metal lines with varying widths. A metal level, therefore, typically comprises a collection of metal lines with line widths ranging from about 1xc3x97 to about 50xc3x97 of the smallest feature size. Such a smallest feature size can be a via having a diameter or cross sectional width of about 0.15 xcexcm to about 10 xcexcm. In implementing Cu metallization in narrow lines, e.g., lines having a width less than about 0.15 xcexcm, it was found that voiding typically occurs after thermal annealing.
Accordingly, there exists a need for methodology enabling implementation of Cu metallization with improved electromigration resistance in relatively wide lines and reduced void generation in relatively narrow lines. There exists a particular need for such Cu metallization methodology in fabricating semiconductor devices having metal levels with varying line widths in the deep sub-micron regime.
An advantage of the present invention is a method of manufacturing a semiconductor device containing Cu metallized interconnection patterns, exhibiting improved electromigration resistance in relatively wide lines and having reduced voids in relatively narrow lines.
Another advantage of the present invention is a semiconductor device having Cu metallized interconnection patterns, exhibiting improved electromigration resistance in relatively wide lines and having reduced voids in relatively narrow lines.
Additional advantages and other features of the present invention will be set forth in the description which follows and in part will be apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a method of manufacturing a semiconductor device, the method comprising: forming a plurality of openings in a dielectric layer, at least one of the openings having a width no greater than a first width and at least one of the openings having a width greater than the first width; depositing a layer of substantially pure copper (Cu) or a first Cu alloy completely filling the at least one opening having a width no greater than the first width and partially filling the at least one opening having a width greater than the first width; and depositing a layer of a second Cu alloy, containing an element in a sufficient amount such that the electromigration resistance of the second Cu alloy is greater than that of substantially pure Cu and greater than that of the first Cu alloy, to completely fill the at least one opening having a width greater than the first width.
Embodiments of the present invention include forming a plurality of small openings having a width up to a designated first width and a plurality of large openings having a width greater than the designated first width, depositing a barrier layer to line the openings, filling the openings, planarizing and depositing a silicon nitride capping layer. Embodiments of the present invention include forming the plurality of openings such that the designated first width is about 5 times the smallest feature size, e.g., an interconnection via having a diameter (or width in cross section) of no greater than about 0.20 micron. Embodiments further include depositing a second Cu alloy that contains an element that imparts electromigration resistance to Cu, such as tin, zinc, strontium, palladium, magnesium, chromium and tantalum. The second Cu alloy can have a resistivity lower than, equal to or greater than the first Cu alloy. Embodiments of the present invention further include performing a first anneal after depositing the substantially pure Cu or first Cu alloy layer and before depositing the second Cu alloy layer, and then performing a second anneal after depositing the second Cu alloy layer, thereby minimizing void formation in narrow lines.
Another aspect of the present invention is a semiconductor device comprising: an interlayer dielectric (ILD); a plurality of trenches in the ILD, the plurality of trenches comprising: a plurality of small openings having a width no greater than a first width; and a plurality of large openings having a width greater than the first width; and metal lines filling the trenches; wherein the metal lines filling the small trenches comprise substantially pure copper (Cu) or a first Cu alloy; and the metal lines filling the large trenches comprise a lower layer of substantially pure Cu or the first Cu alloy and an upper layer of a second Cu alloy on the lower layer, the second Cu alloy containing a sufficient amount of an element such that the electromigration resistance of the second Cu alloy is greater than that of substantially pure Cu and greater than that of the first Cu alloy.
Additional advantages of the present invention will become readily apparent to those skilled in the art from the following detailed description, wherein embodiments of the present invention are described, simply by way of illustration of the best mode contemplated for carrying out the present invention. As will be realized, the present invention is capable of other and different embodiments and its several details are capable of modifications in various obvious respects, all without departing from the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.